This invention relates to the field of data transfer units in which one elements is connected by a common data transfer bus to a series of elements. This invention further relates to the field of multiprocessor systems making use of this type of data transfer unit. High-performance parallel processing systems using a linking network interconnecting plural processors are known in the art In parallel processing, data transfer between each processor is required, and it must be carried out at a high transfer rate and high efficiency. As the degree of parallel processing increases, the linking network between processors increases in size. Accordingly, it is important to reduce to a minimum the number of interconnecting wires required. Further, it is also important to uniquely identify each processor by means of the assignment of processor identification numbers. These identification numbers are used such time as describing the assignment of data to each processor and the transfer of data between each processor. If a data transfer unit employs a certain topology in which a data source is connected by a common bus to plural data destinations, this very much contributes to reducing the number of interconnecting wires required. FIG. 23 outlines the organization of a conventional data transfer unit that uses an address bus to identify each data destination. This conventional data transfer unit comprises a processor element 10, a data bus 40, an address bus 41, and a plurality of input/output (I/0) ports 42. The processor element 10 selects one of the plurality of I/0 ports 42 as the data destination via the address bus 41. Japanese Patent Application, published under Pub. No. 64-62759, shows an example in which an address bus is provided. This application shows a technique in which block numbers are fed to identify each data destination through an address bus, during the broadcasting of data. Meanwhile, there is proposed a technique using no address buses. For instance, Japanese Patent Application, published under Pub. No. 63-44267, discloses a data transfer unit in which one master module is connected by a serial data bus and by a clock signal line to each of a plurality of slave modules. In this application, a header 43, placed at the head of data 44, identifies each data destination (see FIG. 24). Each slave module permits separation of a header 43 from data 44 on the serial data bus, thereby making a decision of whether or not the data 44 is addressed to that slave module from the header 43. Japanese Patent Application, published under Pub. No. 1-283664, is another example in which data accompanied by a header is used. Generally, several ways of setting processor identification numbers have been employed. In one method a host computer sets an identification number to each processor under the host computer's control, and in an other extra hardware for outputting a fixed identification number is provided to every processor.
The foregoing prior art techniques, however, present some drawbacks. For example, the conventional data transfer unit using an address bus to identify each data destination has a problem that the number of interconnecting wires cannot be reduced suitably. Further, another problem will be presented when expanding an existing system. That is, the number of address buslines must be increased.
The conventional data transfer unit in which a header is placed at the head of the data has an advantage that the number of interconnecting wires can be reduced suitably because no address buses are provided. This technique, however, suffers a disadvantage that data cannot be transferred at high speed. The reason for the drop in data transfer rate is the provision of a header which must be placed at the head of each data even when sending out data to the same destination every time, even when sequentially selecting data destinations, or even when carrying out the broadcasting of data.
To sum up, an attempt at reducing the number of interconnecting wires conflicts with accomplishing a high data transfer rate. This means that a conventional multiprocessor, too, suffers from the same problem. Conventional multiprocessor systems have several problems with regard to the way of setting an identification number for each processor. If a host computer sets processor identification numbers, a specialized program is required for the host computer to assign the identification number, otherwise extra hardware for outputting a fixed identification number is required in every processor.